Fabrication of magneto-resistive devices normally involves a sequence of processing steps during which many layers of metals and dielectrics are deposited and then patterned to form a magneto-resistive stack as well as electrodes for electrical connections. The magneto-resistive stack usually includes the free and pinned layers of the device, sandwiched around one or more dielectric layers functioning as the tunnel junction for the magnetic tunnel junction (MTJ) device. To define those millions of MTJ cells in each magnetic random access memory (MRAM) device and make them non-interacting to each other, precise patterning steps including RIE (reactive ion etching) are usually involved. During RIE, high energy ions remove materials vertically in those areas not masked by photoresist, separating one MTJ cell from another.
However, the high energy ions can also react with the non-removed materials laterally. For MTJ cells, this lateral reaction can form a damaged portion by oxygen, moisture and other chemicals on the sidewall, lowering the magneto-resistance ratio and coercivity. This damage is cell size dependent, meaning it becomes more severe when the cell size decreases for the future sub-nano node products. To solve this issue, pure physical etching techniques such as ion beam etching (IBE) have been applied to trim the surface of the MTJ stack to remove the damaged portion. However when trimmed by IBE directly, the volumes of the free layer and pinned layer decrease together, making the latter's size too small to stabilize the internal magnetic state, resulting in a smaller energy barrier and larger switching current. In addition, due to their non-volatile nature, IBE trimmed ferromagnetic materials in the pinned layer and bottom electrode can be re-deposited into the free layer and top electrode, resulting in shorted devices.
Several references teach methods to remove sidewall damage. These include U.S. Patent Applications 2017/0025603 (Nara), 2016/0020386 (Kim et al), and 2006/0132983 (Osugi et al). Other references teach methods of blocking material diffusion into a pinned layer. These include U.S. Patent Application 2016/0211441 (Deshpande et al) and U.S. Patent Application 2012/0012952 (Chen et al). All of these references are different from the present disclosure.